1. Technical Field
The present invention generally relates to semiconductor memories and, in particular, to semiconductor memories having asymmetric column addressing and twisted read write drive (RWD) line architecture.
2. Background Description
It is common for semiconductor memory chip densities to increase by a factor of four with each subsequent generation. As a result, semiconductor memory chips become larger and more difficult to manufacture cost-effectively. As is known, reductions in the number of on-chip control or data signals can directly impact the size of the chip.
FIG. 1 is a block diagram illustrating a Dynamic Random Access Memory (DRAM), according to the prior art. The DRAM includes four units (Unit0, Unit1, Unit2, and Unit3), wherein only one of the four units is accessed as a bank for data read or write operations. More particularly, when a wordline (WL) is activated, the corresponding cells coupled to the wordline are enabled. The data bits read from the cells are amplified by the sense amplifiers and selected by column select line (CSL), which is well known and thus omitted from the Figures for the sake of simplicity. The decoder circuitry for selecting a WL and a CSL are row decoders and column decoders, respectively. The corresponding amplified and selected data bits are then transferred to second sense amplifiers (SSAs) through the master data lines (MDQs).
In this example, only one MDQ line is shown in the array for simplicity. However, the actual array contains a plurality of MDQ lines (i.e., 64) to transfer a plurality of data bits simultaneously. The SSA circuitry amplifies the data bits on the MDQ, and communicates to the DQ circuitry through the data lines.
The data lines that supply data into and drive data from the units are referred to herein as on-chip data lines and also as Read Write Drive (RWD) lines. In this example, the DRAM includes 16 DQs, thus requiring 16 RWD lines to communicate 16 bit data between each unit and the 16 DQ pins. The designation xe2x80x9cDQxe2x80x9d represents the data port of the DRAM in which data is written to, or read from.
Note that laser blowable fuses (fuses) for redundancy replacement are arranged near row decoders and column decoders. Because of the nature of the fuses, wiring over the fuses is not permitted. This makes it difficult to share the data lines between two units.
FIG. 2 is a block diagram illustrating a semiconductor memory architecture that reduces the number of read write drive (RWD) lines by a factor of 2, according to the prior art. The reduction is achieved by twisting the RWD lines to share the RWD lines between the units. Right RWD lines are twisted connecting Unit0 to Unit1 and to Unit3 and twist again as they connect to Unit2. Similarly, eight RWD lines are twisted connecting the Unit1 to Unit0 and to Unit2 and twist again as they connect to Unit3. The conventional semiconductor memory architecture shown in FIG. 2 is described by Kim et al., in xe2x80x9cA 640 MB/s Bi-Directional Data Strobed, Double-Data Rate SDRAM with a 40 mW DLL Circuit for a 256 MB Memory Systemxe2x80x9d, 1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 158-159, Jan. 1998.
However, this article does not describe the idea of asymmetrical addressing. A 2-bit (2b) pre-fetch architecture requires address incrementing, thus requiring proper address assignment to simplify the data bit handling. If addresses are not properly assigned, the twisting of the RWD lines increases the complexity of the peripheral circuitry. Moreover, the article limits the idea of RWD line twisting to 2b prefetch.
An address incremented 2b prefetch architecture is described by Kirihata et al., xe2x80x9cA 220 mm2 256 Mb SDRAM with Single-Sided Stitched WL Architecturexe2x80x9d, 1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 78-79, January 1998. This architecture divides the array into even and odd arrays and, as with the architecture of FIG. 2, also requires an additional set of RWD lines for pre-fetch. This is because the address assignment for incrementing is symmetrical, making RWD line twisting difficult.
Accordingly, there is a need for a semiconductor memory having twisted read write drive (RWD) line architecture and pre-fetch capability. Moreover, there is a need for a semiconductor memory having twisted RWD line architecture and a reduced number of RWD lines.
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture.
The present invention advantageously allows n-bit pre-fetch and the increased performance associated therewith. A further advantage is a reduction in the number of read write drive (RWD) lines (on-chip input/output lines) by a factor of two or more. Another advantage is that the reduced number of RWD lines decreases the length of the semiconductor memory, thus resulting in higher yield and lower manufacturing costs. Yet another advantage is that by sharing the RWD lines, complex data multiplexing logic is eliminated. For example, in the prior art, a series of data multiplexers and logic circuits are necessary to select 16 of the 32 RWD lines.
According to a first aspect of the invention, there is provided a method for reducing read write drive (RWD) lines in a semiconductor memory having a plurality of memory units. Each of the plurality of memory units includes a plurality of columns. The method includes the step of twisting the RWD lines horizontally and/or vertically such that the RWD lines are shared between the plurality of memory units. Each of the plurality of columns included in each of the plurality of memory units are asymmetrically arranged, so as to provide access to the RWD lines through asymmetrical addressing.
According to a second aspect of the invention, the arranging step includes the step of asymmetrically arranging each of the plurality of columns such that a column in one of the plurality of memory units is disposed above or below another column in another one of the plurality of memory units, the column and the other column being asymmetric with respect to accessing the RWD lines through even addresses and odd addresses.
According to a third aspect of the invention, the RWD lines include even RWD lines and odd RWD lines, and the arranging step shares the even RWD lines and the odd RWD lines between the plurality of memory units.
According to a fourth aspect of the invention, the arranging step further includes the step of restricting opposing columns from having a same pre-fetch addressing.
According to a fifth aspect of the invention, the plurality of RWD lines include orthogonal or diagonal metal lines.
According to a sixth aspect of the invention, the semiconductor memory further includes a fuse bank, and the method further includes the step of dividing the fuse bank to provide space for implementing the twisting step.
According to a seventh aspect of the invention, there is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns are included in each of the plurality of memory units, each of the plurality of columns being adapted to access the plurality of RWD lines through asymmetrical addressing.
According to an eighth aspect of the invention, each of the plurality of columns are asymmetrically arranged such that a column in one of the plurality of memory units is disposed above or below another column in another one of the plurality of memory units, the column and the other column being asymmetric with respect to accessing the RWD lines through even addresses and odd addresses.
According to a ninth aspect of the invention, the RWD lines include even RWD lines and odd RWD lines, and the arranging step shares the even RWD lines and the odd RWD lines between the plurality of memory units.
According to a tenth aspect of the invention, opposing columns are restricted from having a same pre-fetch addressing.
According to an eleventh aspect of the invention, the plurality of RWD lines include orthogonal or diagonal metal lines.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.